The present invention relates to monolithic, large-scale integrated semiconductor circuit structures and particularly to such structures having arrays of logic circuit cells. The invention especially addresses novel layouts of the cell arrays in combination with layouts of the overlying metallization utilized to provide voltage level supplies to the cells, interconnect cells and intraconnect the semiconductor devices forming the particular circuit cell.
With the ever-increasing microminiaturization of integrated circuits and the attendant increased density of such circuits in large-scale integrated circuits, the arrangement of the metallization pattern utilized to intraconnect within cells, interconnect cells and provide the voltage supply distribution to the respective cells has been becoming increasingly difficult. It is regarded highly desirable within the art to utilize as few levels of metallization as possible separated by insulative layers. It is also considered to be very desirable to have the integrated circuit devices and metallizations laid out in such a fashion that design automation as well as computer-aided design of integrated circuits would be facilitated.